> 	Could someone who knows comment on why the 4m microsparc
> data/instruction caches are disabled?  I looked at the code in
> cache.c and it appears to be some detection conflict between
> 4m microsparcs and 4m supersparcs.

The CPU/cache detection code is in need of some serious cleanup (and it
is being worked on).

Currently, on a microsparc II, the cache enable/disable bits in the
mmu control register aren't touched. This means that the cache isn't
enabled explicitly, but it isn't _disabled_ explicitly either.

Since the PROM turns on the cache before handing control to the NetBSD
kernel, the caches remain enabled while NetBSD runs. MicrosparcII cache
flushing/invalidating is handled appropriately, though, in -current.

-pk