Subject: NetBSD/sparc and Cycle-5.
To: None <port-sparc@NetBSD.ORG>
From: Tom Backman <tom@stacken.kth.se>
List: port-sparc
Date: 01/21/1997 22:39:07
I recently helped with the upgrade of a sparc upgraded with a Cycle-5 board.

The machine works fine with NetBSD-1.2, but i wonder a bit about the cache.
the kernel gives this message at boot:

cpu0: physical 16K instruction (32 b/l), 8K data (16 b/l) cache NOT enabled for
4/0 cpu/mmu combination

The machine used to run Sunos 4.1.3, and it feels like the speed is abt the
same at the moment anyway, but if there is a way to get the cache to work,
it would be nice.

/ Tom