On Wed, 16 Oct 1996 20:32:40 -0700 
 Pavlin Ivanov Radoslavov <pavlin@catarina.usc.edu> wrote:

 > using 400 buffers containing 1638400 bytes of memory
 > bootpath:....
 > mainbus0 (root): SUNW,SPARCstation-10
 > cpu0 at mainbus0: TI, TMS390Z50 @ 36MHz, on-chip FPU
 > cpu0: physical cache enabledon (64 b/l), 16K data (32 b/l)
 > trap type 0x7: pc=f8024e24 npc=f8024e28 psr=41401fc7<EF,S,PS>
 > panic: alignment fault
 > halted
 > 
 > It has a SuperSPARC processor, but I am not sure about the MXCC cache
 > (unless you want me to disassemble everything :-)) If the lack of
 > MXCC is the reason, when approximately this patch will be available.

This looks a lot like my SS10 which has a similar problem (mine
just hangs ... at least you panic :-)

The patch I use is below... I'll clean it up and commit it as an
interim to Aaron making the auto-detect work...

(Remember, this is a hack... :-)

Jason R. Thorpe                                       thorpej@nas.nasa.gov
NASA Ames Research Center                               Home: 408.866.1912
NAS: M/S 258-6                                          Work: 415.604.0935
Moffett Field, CA 94035                                Pager: 415.428.6939

 ----- snip -----

Index: cache.c
===================================================================
RCS file: /mastersrc/netbsd/src/sys/arch/sparc/sparc/cache.c,v
retrieving revision 1.1.1.7
retrieving revision 1.5
diff -c -r1.1.1.7 -r1.5
*** cache.c	1996/10/15 21:59:28	1.1.1.7
--- cache.c	1996/10/16 02:42:16	1.5
***************
*** 75,80 ****
--- 75,93 ----
  int cache_alias_bits;
  #endif
  
+ #if defined(SUN4M)
+ /*
+  * XXX The cache on dufus.nas.nasa.gov doesn't work like any other
+  * XXX SS10 cache I've ever seen.  This option allows easy disabling
+  * XXX of the cache before boot time with a patch.
+  */
+ #if defined(SUN4M_NO_CACHE_ENABLE)
+ int	sun4m_no_cache_enable = 1;
+ #else
+ int	sun4m_no_cache_enable = 0;
+ #endif /* SUN4M_NO_CACHE_ENABLE */
+ #endif /* SUN4M */
+ 
  /*
   * A few quick macros to allow for different ASI's between 4M/4/4C machines
   */
***************
*** 123,128 ****
--- 136,147 ----
  	ts = cacheinfo.c_totalsize;
  
  	if (CPU_ISSUN4M) {
+ #ifdef SUN4M
+ 		if (sun4m_no_cache_enable) {
+ 			printf("cache NOT enabled\n");
+ 			return;
+ 		}
+ #endif
  		i = lda(SRMMU_PCR, ASI_SRMMU);
  		switch (mmumod) {
  		case SUN4M_MMU_HS:	/* HyperSPARC */