I plan to sync the sparc's pmap stuff with some of the 3-level MMU
support for sun4/400 models that I've been working on lately.

This has some implications for all sun4 ports: pmap's notion of the
virtual address space has been converted to a 3-level design for all
cpu models (the levels are called "region", "segment" and "page table").
On machines with a 2 level MMU, the region and segment parts "collapse"
into the hardware "pmeg" table.

This all makes for more complex pmap code. But there's an advantage too:
demand for hardwired memory to hold a process' mmu data structures is
now much less because it can be dealt with a region at a time (one region
describes 16M worth of virtual address space). A typical program will 
consists off just two (statically linked) or three (dynamically linked)
regions for which the pmap structures will fit well within one page.

-pk