>    Anyway, I'm building --current on a sparc here following Alistair's
   >    build recipe.  Apart from commenting out the fdc0 and fd* in sparc
   >    kernel's all seems well.
   > 
   > hmm.. my sparc doesn't have problems with this.. maybe it's beacuse it
   > doesn't have a floopy drive on the machine at all (elc), it does probe
   > for it and say "not configured" at boot time (like it always has done..)
   >    
   
   I'm seeing a bit of weirdness on elc's: the PROM reports an `fd' device, but
   when I try to actually access the chip I get non-sense (ie. reading its
   registers result in 0xff as if there's no chip there though I would expect
   a bus error if that's the case).
   
   I also noted that sjg's SS2 probed the chip to be a 82077...

i've recently rebuilt my kernel with the fd options to see what happened
there.  i saw this:

Copyright (c) 1982, 1986, 1989, 1991, 1993
        The Regents of the University of California.  All rights reserved.

NetBSD 1.0A (_splode_) #152: Mon Mar 20 23:45:07 EST 1995
    mrg@splode.mame.mu.OZ.AU:/splode/build/src/sys/arch/sparc/compile/_splode_
real mem = 16588800
avail mem = 14352384
using 202 buffers containing 827392 bytes of memory
mainbus0 (root)
cpu0 at mainbus0: SUNW,Sun 4/25 (W8601/8701 or MB86903 @ 33 MHz, on-chip FPU)
cpu0: cache chip bug; trap page uncached
cpu0: 65536 byte write-through, 32 bytes/line, hw flush cache enabled
memreg0 at mainbus0 ioaddr 0xf4000000
clock0 at mainbus0 ioaddr 0xf2000000: mk48t02 (eeprom)
timer0 at mainbus0 ioaddr 0xf3000000
auxreg0 at mainbus0 ioaddr 0xf7400003
zs0 at mainbus0 ioaddr 0xf1000000 pri 12, softpri 6
zs1 at mainbus0 ioaddr 0xf0000000 pri 12, softpri 6
audio0 at mainbus0 ioaddr 0xf7201000 pri 13, softpri 4
sbus0 at mainbus0 ioaddr 0xf8000000: clock = 20 MHz
dma0 at sbus0 slot 0 offset 0x400000: rev 1+
esp0 at sbus0 slot 0 offset 0x800000 pri 3: ESP100 20Mhz, target 7
scsibus0 at esp0
esp0 targ 0 lun 0: <SEAGATE, ST1480   SUN0424, 7516> SCSI2 0/direct fixed
sd0 at scsibus0: 411MB, 1476 cyl, 9 head, 63 sec, 512 bytes/sec
le0 at sbus0 slot 0 offset 0xc00000 pri 5: hardware address 08:00:20:03:99:c6
bwtwo0 at sbus0 slot 3 offset 0x0: SUNW,501-1561, 1152 x 900 (console)
fdc0 at mainbus0 ioaddr 0xf720000

except the cursor was hanging on the end of the last line, not on
the next, so when the `Automatic reboot in progress...' line came
on, it was on the end of this.

this is on a sparc elc.

.mrg.