A clock divisor of 1 is `not recommended' in the Zilog manual.
Presumably this is for the same reason as on any serial port:
with a x16 or x64 clock, the sample can be taken at the mid-point
of the bit time, so that any cable delays or clock skew will not
goof up the bit pattern you get from the RS232 line.  With a x1
clock, this is no longer possible (well, you could have an internal
clock doubler and divide it back down, or use a two-phase clock,
but the zscc does neither).

Chris

------------------------------------------------------------------------------