I am currently responsible for getting the PCMCIA bus working on our product
which contains an Hitachi SH4, chip version: HD6417750, OC1M, BP200.

We have found that the timing waveforms for the PCMCIA interface are NOT
fully PCMCIA2.1 compliant. In fact, we can only get 8bit mode working. 16bit
mode accesses to the common memory area of the PCMCIA card does not work
100%.

The problem is with the HOLD time between the read enable line going high
and the chip select line going high. There should be a gap of around 30ns
between the read enable going high and the chip select going high.
             
Our version of the SH4 causes the chip select and the read enable to go high
at exactly the same time. This is not compliant with PCMCIA
specifications(!)

We have used a hardware fix to solve the problem by regenerating the read
enable 30ns before the chip select. We understand that the 7750S version of
the SH4 fixes this problem, but it is not readily available ...

Has anyone else had this same problem? How did you manage to work around
this problem?

Aras Vaichas


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