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After Garrett imported the new atheros HAL and said he would like to see
test results on non-alchemy mips plattforms, I moved a PCI ath card to my
O2.

The good news: ath0 works fine and connects to my AP with wpa.

The bad news: it needs some bus_space_*_stream_* functions that we currently
do not implement. I do not knowing anything about sgimips hardware or the
bus_space_tag_t constants used in the exisiting code, so I was not able to
come up with a proper fix ready to commit - in this case I only care about
PCI access, so the always-swapping hack attached worked for me.

Anyone could offer a real implementation? Or provide some background
about the various bus_space_tag_t (and their endianess)?

Martin

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Index: include/bus.h
===================================================================
RCS file: /cvsroot/src/sys/arch/sgimips/include/bus.h,v
retrieving revision 1.20
diff -c -u -p -r1.20 bus.h
--- include/bus.h	26 May 2006 13:23:34 -0000	1.20
+++ include/bus.h	5 Jun 2006 23:46:01 -0000
@@ -151,6 +151,19 @@ u_int32_t bus_space_read_4(bus_space_tag
 u_int64_t bus_space_read_8(bus_space_tag_t, bus_space_handle_t, bus_size_t);
 
 /*
+ *	u_intN_t bus_space_read_stream_N(bus_space_tag_t tag,
+ *	    bus_space_handle_t bsh, bus_size_t offset);
+ *
+ * Read a 1, 2, 4, or 8 byte quantity from bus space
+ * described by tag/handle/offset, but w/o any byte order changes.
+ */
+
+u_int8_t bus_space_read_stream_1(bus_space_tag_t, bus_space_handle_t, bus_size_t);
+u_int16_t bus_space_read_stream_2(bus_space_tag_t, bus_space_handle_t, bus_size_t);
+u_int32_t bus_space_read_stream_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);
+u_int64_t bus_space_read_stream_8(bus_space_tag_t, bus_space_handle_t, bus_size_t);
+
+/*
  *	void bus_space_read_multi_N(bus_space_tag_t tag,
  *	    bus_space_handle_t bsh, bus_size_t offset,
  *	    u_intN_t *addr, size_t count);
@@ -246,6 +259,24 @@ void	bus_space_write_8(bus_space_tag_t, 
 	    u_int64_t);
 
 /*
+ *	void bus_space_write_stream_N(bus_space_tag_t tag,
+ *	    bus_space_handle_t bsh, bus_size_t offset,
+ *	    u_intN_t value);
+ *
+ * Write the 1, 2, 4, or 8 byte value `value' to bus space
+ * described by tag/handle/offset. Do not adjust byte order.
+ */
+
+void	bus_space_write_stream_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
+	    u_int8_t);
+void	bus_space_write_stream_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
+	    u_int16_t);
+void	bus_space_write_stream_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
+	    u_int32_t);
+void	bus_space_write_stream_8(bus_space_tag_t, bus_space_handle_t, bus_size_t,
+	    u_int64_t);
+
+/*
  *	void bus_space_write_multi_N(bus_space_tag_t tag,
  *	    bus_space_handle_t bsh, bus_size_t offset,
  *	    const u_intN_t *addr, size_t count);
Index: sgimips/bus.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sgimips/sgimips/bus.c,v
retrieving revision 1.45
diff -c -u -p -r1.45 bus.c
--- sgimips/bus.c	16 Apr 2006 16:39:37 -0000	1.45
+++ sgimips/bus.c	5 Jun 2006 23:46:01 -0000
@@ -212,6 +212,12 @@ bus_space_read_4(bus_space_tag_t tag, bu
 	return reg;
 }
 
+u_int32_t
+bus_space_read_stream_4(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t o)
+{
+	return le32toh(bus_space_read_4(tag, bsh, o));
+}
+
 void
 bus_space_write_4(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t o, u_int32_t v)
 {
@@ -232,6 +238,12 @@ bus_space_write_4(bus_space_tag_t tag, b
 	}
 }
 
+void
+bus_space_write_stream_4(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t o, u_int32_t v)
+{
+	bus_space_write_4(tag, bsh, o, htole32(v));
+}
+
 #if defined(MIPS3)
 u_int64_t
 bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t o)

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