In article <5wLGf1l2.1134526522.0369540.wileyc@localhost>
wileyc@rezrov.net wrote:

> >BTW, where does this 0x800000 come from?
> >Hardware (crime) limitation?
> >Or software boundary to store kernel into the lower 8MB region?
> 
> Apparently all DMA buffers must be above 8MB, per Jeff Smith's
> explanation of the IRIX workarounds.

I can't see why allocating DMA buffers above 8MB could fix the race.

Jeff wrote in his post:
>> The agent chip does not allow K0 access above
>> 8MB.  They do this by having the kernel map
>> everything else in K2 and use a different cache
>> mode the K0 is set to.

Does this mean that kernel shouldn't (or can't?) access KSEG0
higher than 8MB and should use KSEG2 mapings to access RAMs
above PA 0x800000?
If so, I'm afraid it's not easy to adapt our kernel to the restriction
because current mips pmap assumes all RAMs can be accessed via KSEG0.

A possible easy workaround is to prepare DMA bounce buffer which
should never be accessed via KSEG0, but of cource it cause performance
penalty on copying data in bus_dmamap_sync(9).
---
Izumi Tsutsui