On Fri, Apr 02, 2004 at 10:32:35PM +0200, Manuel Bouyer wrote:

> spurious interrupt, ipending c000

That's MIPS_INT_MASK_5 and MIPS_INT_MASK_4, which are timer and buserror
interrupts respectively.

Hmmm, it looks like the buserror handler isn't actually being hooked into
the interrupt routine.  Try the patch below and let me know what happens.

(it would be interesting to find out _why_ you're receiving a bus error in
the first place :)

-- Chris
	GPG key FEB9DE7F (91AF 4534 4529 4BCC 31A5  938E 023E EEFB FEB9 DE7F)


Index: imc.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sgimips/dev/imc.c,v
retrieving revision 1.16
diff -u -r1.16 imc.c
--- imc.c	18 Jan 2004 13:11:18 -0000	1.16
+++ imc.c	3 Apr 2004 00:27:35 -0000
@@ -58,7 +58,7 @@
 static void	imc_attach(struct device *, struct device *, void *);
 static int	imc_print(void *, const char *);
 void		imc_bus_reset(void);
-void		imc_bus_error(void);
+void		imc_bus_error(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
 void		imc_watchdog_reset(void);
 void		imc_watchdog_disable(void);
 void		imc_watchdog_enable(void);
@@ -132,8 +132,10 @@
 	printf("\n");
 
 	/* Clear CPU/GIO error status registers to clear any leftover bits. */
-	bus_space_write_4(isc.iot, isc.ioh, IMC_CPU_ERRSTAT, 0);
-	bus_space_write_4(isc.iot, isc.ioh, IMC_GIO_ERRSTAT, 0);
+	imc_bus_reset();
+
+	/* Hook the bus error handler into the ISR */
+	platform.intr4 = imc_bus_error;
 
 	/*
 	 * Enable parity reporting on GIO/main memory transactions.
@@ -249,7 +251,7 @@
 }
 
 void
-imc_bus_error(void)
+imc_bus_error(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
 {
 	printf("bus error: cpu_stat %08x addr %08x, gio_stat %08x addr %08x\n",
 			bus_space_read_4(isc.iot, isc.ioh, IMC_CPU_ERRSTAT),