Subject: Re: netbsd on r5000 indy
To: Christopher SEKIYA <wileyc@rezrov.net>
From: Manuel Bouyer <bouyer@antioche.eu.org>
List: port-sgimips
Date: 01/29/2003 21:31:15
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On Wed, Jan 29, 2003 at 11:58:15PM +0900, Christopher SEKIYA wrote:
> On Tue, Jan 28, 2003 at 03:49:20PM +0100, Manuel Bouyer wrote:
>
> > cpu0: 512KB/32B direct-mapped write-back L2 Data cache
> > cpu0: disabling IP22 SysAD L2 cache
>
> > panic: TLB out of universe: ksp 0xc59abb98 epc 0x8829b15c vaddr 0xffffe000
> > Stopped in pid 1 (init) at 0x88291b14: jr ra
> > bdslot: nop
>
> L2 cache brokenness. The following _may_ help:
>
> * apply the patch appended, which enables r5k L2 cache support,
> * fixup sgimips/sgimips/machdep.c/mips_machdep_cache_config() such that
> the (mach_type == MACH_SGI_IP22) does the same as the #ifdef 1 bit
> for the MACH_SGI_IP32 code.
Wow, this seems to work. The patch alone looks to be enouth, the change
to mips_machdep_cache_config() doens't seem to be necessary:
>> boot -f bootp()netbsd.ecoff
Obtaining netbsd.ecoff from server juliard.antioche.eu.org
2899360+0+244860 entry: 0x88069000
[ no symbols available ]
IOC rev 1, machine Indy (Guiness), board rev 3
Timer calibration, got 750000 cycles (750000, 750000, 750000)
CPU clock speed = 150.00Mhz
zs channel 0 had address 0xbfbd9830
R5000/Rm5200 SCACHE
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
NetBSD 1.6L (GENERIC_INDY) #2: Wed Jan 29 21:24:38 CET 2003
bouyer@pop:/local/pop1/bouyer/current/src/sys/arch/sgimips/compile/GENERIC_INDY
65536 KB memory, 56508 KB free, 768 KB for ARCS, 3376 KB in 844 buffers
mainbus0 (root): SGI-IP22 [SGI, 6906de17], 1 processor
cpu0 at mainbus0: MIPS R5000 CPU (0x2310) Rev. 1.0 with built-in FPU Rev. 1.0
cpu0: 32KB/32B 2-way set-associative L1 Instruction cache, 48 TLB entries
cpu0: 32KB/32B 2-way set-associative write-back L1 Data cache
cpu0: 512KB/32B direct-mapped write-back L2 Data cache
cpu0: disabling IP22 SysAD L2 cache
imc0 at mainbus0 addr 0x1fa00000
imc0: Revision 3
gio0 at imc0
hpc0 at gio0 addr 0x1fb80000: SGI HPC3
zsc0 at hpc0 offset 0x59830
zstty0 at zsc0 channel 1 (console i/o)
zstty1 at zsc0 channel 0
sq0 at hpc0 offset 0x54000: SGI Seeq 80c03
sq0: Ethernet address 08:00:69:06:de:17
wdsc0 at hpc0 offset 0x44000: WD33C93B SCSI, rev=0, target 7
scsibus2 at wdsc0: 8 targets, 8 luns per target
dsclock0 at hpc0 offset 0x60000
biomask 07 netmask 07 ttymask 0f clockmask bf
scsibus2: waiting 2 seconds for devices to settle...
sd0 at scsibus2 target 3 lun 0: <QUANTUM, FIREBALL ST3.2S, 0F0C> disk fixed
sd0: 3090 MB, 7068 cyl, 4 head, 223 sec, 512 bytes/sect x 6328861 sectors
sd0: sync (200.0ns offset 12), 8-bit (5.000MB/s) transfers, tagged queueing
boot device: sd0
root on sd0a dumps on sd0b
root file system type: ffs
Enter pathname of shell or RETURN for /bin/sh:
We recommend creating a non-root account and using su(1) for root access.
#
The machine has run a sup to completion, and will now start a build.sh.
Attached are the diffs that produced the working kernel.
--
Manuel Bouyer <bouyer@antioche.eu.org>
NetBSD: 24 ans d'experience feront toujours la difference
--
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Content-Disposition: attachment; filename=sgimips-patch
Index: arch/mips/conf/files.mips
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/conf/files.mips,v
retrieving revision 1.45
diff -u -r1.45 files.mips
--- arch/mips/conf/files.mips 2002/11/15 01:02:49 1.45
+++ arch/mips/conf/files.mips 2003/01/29 20:16:51
@@ -45,6 +45,7 @@
file arch/mips/mips/cache_tx39_subr.S mips1 & enable_mips_tx3900
file arch/mips/mips/cache_r4k.c mips3 | mips4
file arch/mips/mips/cache_r5k.c mips3 | mips4
+file arch/mips/mips/cache_r5k_subr.S mips3 | mips4
file arch/mips/mips/cache_r5900.c mips3 & mips3_5900
file arch/mips/mips/cache_mipsNN.c mips32 | mips64
Index: arch/mips/include/cache_r4k.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/cache_r4k.h,v
retrieving revision 1.8
diff -u -r1.8 cache_r4k.h
--- arch/mips/include/cache_r4k.h 2002/11/17 06:40:43 1.8
+++ arch/mips/include/cache_r4k.h 2003/01/29 20:16:51
@@ -357,29 +357,6 @@
void r4k_pdcache_inv_range_32(vaddr_t, vsize_t);
void r4k_pdcache_wb_range_32(vaddr_t, vsize_t);
-void r5k_icache_sync_all_32(void);
-void r5k_icache_sync_range_32(vaddr_t, vsize_t);
-void r5k_icache_sync_range_index_32(vaddr_t, vsize_t);
-
-void r5k_pdcache_wbinv_all_16(void);
-void r5k_pdcache_wbinv_all_32(void);
-void r4600v1_pdcache_wbinv_range_32(vaddr_t, vsize_t);
-void r4600v2_pdcache_wbinv_range_32(vaddr_t, vsize_t);
-void vr4131v1_pdcache_wbinv_range_16(vaddr_t, vsize_t);
-void r5k_pdcache_wbinv_range_16(vaddr_t, vsize_t);
-void r5k_pdcache_wbinv_range_32(vaddr_t, vsize_t);
-void r5k_pdcache_wbinv_range_index_16(vaddr_t, vsize_t);
-void r5k_pdcache_wbinv_range_index_32(vaddr_t, vsize_t);
-
-void r4600v1_pdcache_inv_range_32(vaddr_t, vsize_t);
-void r4600v2_pdcache_inv_range_32(vaddr_t, vsize_t);
-void r5k_pdcache_inv_range_16(vaddr_t, vsize_t);
-void r5k_pdcache_inv_range_32(vaddr_t, vsize_t);
-void r4600v1_pdcache_wb_range_32(vaddr_t, vsize_t);
-void r4600v2_pdcache_wb_range_32(vaddr_t, vsize_t);
-void r5k_pdcache_wb_range_16(vaddr_t, vsize_t);
-void r5k_pdcache_wb_range_32(vaddr_t, vsize_t);
-
void r4k_sdcache_wbinv_all_32(void);
void r4k_sdcache_wbinv_range_32(vaddr_t, vsize_t);
void r4k_sdcache_wbinv_range_index_32(vaddr_t, vsize_t);
Index: arch/mips/include/cpuregs.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/cpuregs.h,v
retrieving revision 1.59
diff -u -r1.59 cpuregs.h
--- arch/mips/include/cpuregs.h 2003/01/10 03:22:48 1.59
+++ arch/mips/include/cpuregs.h 2003/01/29 20:16:51
@@ -325,6 +325,9 @@
/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
#define MIPS3_CONFIG_SE 0x00001000
+/* L2 cache-present bit for 5000SC */
+#define MIPS3_CONFIG_SC_ENABLE 0x00001000
+
/* Block ordering: 0: sequential, 1: sub-block */
#define MIPS3_CONFIG_EB 0x00002000
Index: arch/mips/mips/cache.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/cache.c,v
retrieving revision 1.16
diff -u -r1.16 cache.c
--- arch/mips/mips/cache.c 2003/01/10 03:22:49 1.16
+++ arch/mips/mips/cache.c 2003/01/29 20:16:51
@@ -82,7 +82,8 @@
#endif
#ifdef MIPS3_PLUS
-#include <mips/cache_r4k.h> /* includes r5k and greater */
+#include <mips/cache_r4k.h>
+#include <mips/cache_r5k.h>
#endif
#if defined(MIPS32) || defined(MIPS64)
@@ -644,10 +645,6 @@
#ifdef ENABLE_MIPS_R4700
case MIPS_R4700:
#endif
-#ifndef ENABLE_MIPS_R3NKK
- case MIPS_R5000:
-#endif
- case MIPS_RM5200:
switch (mips_sdcache_ways) {
case 1:
switch (mips_sdcache_line_size) {
@@ -701,6 +698,22 @@
panic("r4k sdcache %d way line size %d",
mips_sdcache_ways, mips_sdcache_line_size);
}
+ break;
+#ifndef ENABLE_MIPS_R3NKK
+ case MIPS_R5000:
+#endif
+ case MIPS_RM5200:
+ printf("R5000/Rm5200 SCACHE\n");
+ mips_cache_ops.mco_sdcache_wbinv_all =
+ r5k_sdcache_wbinv_all;
+ mips_cache_ops.mco_sdcache_wbinv_range =
+ r5k_sdcache_wbinv_range;
+ mips_cache_ops.mco_sdcache_wbinv_range_index =
+ r5k_sdcache_wbinv_rangeall; /* XXX? */
+ mips_cache_ops.mco_sdcache_inv_range =
+ r5k_sdcache_wbinv_range;
+ mips_cache_ops.mco_sdcache_wb_range =
+ r5k_sdcache_wb_range;
break;
#endif /* MIPS3 || MIPS4 */
Index: arch/mips/mips/cache_r5k.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/cache_r5k.c,v
retrieving revision 1.6
diff -u -r1.6 cache_r5k.c
--- arch/mips/mips/cache_r5k.c 2002/11/07 23:03:21 1.6
+++ arch/mips/mips/cache_r5k.c 2003/01/29 20:16:51
@@ -39,6 +39,7 @@
#include <mips/cache.h>
#include <mips/cache_r4k.h>
+#include <mips/cache_r5k.h>
#include <mips/locore.h>
/*
@@ -581,3 +582,57 @@
#undef trunc_line16
#undef round_line
#undef trunc_line
+
+/*
+ * Cache operations for R5000-style secondary caches:
+ *
+ * - Direct-mapped
+ * - Write-through
+ * - Physically indexed, physically tagged
+ *
+ */
+
+
+__asm(".set mips3");
+
+#define R5K_Page_Invalidate_S 0x17
+
+void
+r5k_sdcache_wbinv_all(void)
+{
+ vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
+ vaddr_t eva = va + mips_sdcache_size;
+
+ while (va < eva) {
+ cache_op_r4k_line(va, R5K_Page_Invalidate_S);
+ va += (128 * 32);
+ }
+}
+
+/* XXX: want wbinv_range_index here instead? */
+void
+r5k_sdcache_wbinv_rangeall(vaddr_t va, vsize_t size)
+{
+ r5k_sdcache_wbinv_all();
+}
+
+#define round_page(x) (((x) + (128 * 32 - 1)) & ~(128 * 32 - 1))
+#define trunc_page(x) ((x) & ~(128 * 32 - 1))
+
+void
+r5k_sdcache_wbinv_range(vaddr_t va, vsize_t size)
+{
+ vaddr_t eva = round_page(va + size);
+ va = trunc_page(va);
+
+ while (va < eva) {
+ cache_op_r4k_line(va, R5K_Page_Invalidate_S);
+ va += (128 * 32);
+ }
+}
+
+void
+r5k_sdcache_wb_range(vaddr_t va, vsize_t size)
+{
+ /* Write-through cache, no need to WB */
+}
Index: arch/mips/mips/pmap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/pmap.c,v
retrieving revision 1.145
diff -u -r1.145 pmap.c
--- arch/mips/mips/pmap.c 2003/01/06 20:30:32 1.145
+++ arch/mips/mips/pmap.c 2003/01/29 20:16:51
@@ -266,7 +266,6 @@
void mips_dump_segtab(struct proc *);
#endif
-#if defined(MIPS3_L2CACHE_ABSENT)
/*
* Flush virtual addresses associated with a given physical address
*/
@@ -290,7 +289,6 @@
}
#endif
}
-#endif /* MIPS3_L2CACHE_ABSENT */
/*
* Bootstrap the system enough to run with virtual memory.
@@ -1578,6 +1576,14 @@
mips_pagezero((caddr_t)MIPS_PHYS_TO_KSEG0(phys));
+#if 1 /* XXXrkb: R5kSC hacks */
+ mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(phys), NBPG);
+#endif
+
+#if 1 /* XXXrkb: R5kSC hacks */
+ mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(phys), NBPG);
+#endif
+
#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT) /* XXX mmu XXX */
/*
* If we have a virtually-indexed, physically-tagged WB cache,
@@ -1611,6 +1617,16 @@
printf("pmap_copy_page(%lx) dst nonphys\n", (u_long)dst);
#endif
+#if 1 /* XXXrkb: R5kSC hacks */
+ mips_flushcache_allpvh(src);
+/* mips_flushcache_allpvh(dst); */
+#endif
+
+#if 1 /* XXXrkb: R5kSC hacks */
+ mips_flushcache_allpvh(src);
+/* mips_flushcache_allpvh(dst); */
+#endif
+
#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT) /* XXX mmu XXX */
/*
* If we have a virtually-indexed, physically-tagged cache,
@@ -1634,6 +1650,16 @@
mips_pagecopy((caddr_t)MIPS_PHYS_TO_KSEG0(dst),
(caddr_t)MIPS_PHYS_TO_KSEG0(src));
+
+#if 1 /* XXXrkb: R5kSC hacks */
+ mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(src), NBPG);
+ mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(dst), NBPG);
+#endif
+
+#if 1 /* XXXrkb: R5kSC hacks */
+ mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(src), NBPG);
+ mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(dst), NBPG);
+#endif
#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT) /* XXX mmu XXX */
/*
Index: arch/sgimips/sgimips/machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/sgimips/sgimips/machdep.c,v
retrieving revision 1.49
diff -u -r1.49 machdep.c
--- arch/sgimips/sgimips/machdep.c 2003/01/10 03:48:40 1.49
+++ arch/sgimips/sgimips/machdep.c 2003/01/29 20:16:53
@@ -71,7 +71,7 @@
#include <mips/locore.h>
#include <mips/cache.h>
-#if 0
+#if 1
#include <mips/cache_r5k.h>
#endif
@@ -917,7 +917,7 @@
if (mach_type == MACH_SGI_IP32)
{
-#if 1
+#if 0
/* L2 cache does not work on IP32 (yet) */
mips_sdcache_size = 0;
mips_sdcache_line_size = 0;
@@ -942,7 +942,18 @@
else /* IP22 works, maybe */
{
arcbios_tree_walk(mips_machdep_find_l2cache, NULL);
+#if 0
+ cpu_config = mips3_cp0_config_read();
+ printf("\nbefore mips_machdep_cache_config: SE = %x\n",
+ cpu_config & MIPS3_CONFIG_SE);
+
+ r5k_enable_sdcache();
+
+ cpu_config = mips3_cp0_config_read();
+ printf("after mips_machdep_cache_config: SE = %x\n",
+ cpu_config & MIPS3_CONFIG_SE);
}
+#endif
}
void
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