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In message <20030129145815.GC297@rezrov.net>, you write: 

-> On Tue, Jan 28, 2003 at 03:49:20PM +0100, Manuel Bouyer wrote:
-> 
-> > cpu0: 512KB/32B direct-mapped write-back L2 Data cache
-> > cpu0: disabling IP22 SysAD L2 cache
-> 
-> > panic: TLB out of universe: ksp 0xc59abb98 epc 0x8829b15c vaddr 0xffffe000
-> > Stopped in pid 1 (init) at      0x88291b14:     jr      ra
-> >                 bdslot: nop
-> 
-> L2 cache brokenness.  The following _may_ help:

I had that same gut instinct, but on the IP22, the external cache isn't 
driven by the CPU directly, but rather via access to magick registers 
somewhere in 64-bit space.  I had Manuel try just the pmap.c patches
to compensate for lack of VCE avoidance, but that didn't help.. I've
got a trace and symbols for Manuel's kernel, so I'll try and look at
it probably over the weekend (ENOTIME this week 8-/).

-> * fixup sgimips/sgimips/machdep.c/mips_machdep_cache_config() such that
->   the (mach_type == MACH_SGI_IP22) does the same as the #ifdef 1 bit
->   for the MACH_SGI_IP32 code.
-> 
-> Just a guess.

It probably can't hurt to try, but I don't think the R5k in the Indy works
like that.  

--rafal

----
Rafal Boni                                              rafal.boni@eDial.com
 PGP key C7D3024C, print EA49 160D F5E4 C46A 9E91  524E 11E0 7133 C7D3 024C


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