>-> >    I note that the MACE RTC driver seems to be particularly busted,
>->
>-> (snip)
>->
>-> > mcclock0 at mace0 offset 0x3a0000
>->
>-> That should be 0x3a0007, per experimental evidence.

It means (legacy) 8bit device is wired at double word (64bit) stride in processor
address space.   If the hardware circuit is designed correctly, LD or SD instruction
do handsome work in endian neutral way.  With sub-word manipulation (LB/SB),
you need to do +7 for BE arrangement...

Toru Nishimura/ALKYL Technology