> FWIW, IDT's R5000 docs are still online at:

Um,  mystery insolved.   The IDT does not mention about the
secondary cache tag design and how addess coded performed.
RM5200 UM describes the 2ndary cache architecture in defnite
figures.   I can see R5000 SC controlling pin out is identical to
RM527x.  On the other hand, JP version of NEC Vr5000
provides (very confusing) 2nd cache tag figure which does not
match to RM527x.

Toru Nishimura/ALKYL Technology