Rafal Boni rafal@attbi.com said;

> Also, the new R5000SC cache code seems broken (though
> Chris did warn about known issues with it), and gives the following
> output on my newly upgraded (to R5000SC) O2:
>
> CPU clock speed = 180.00Mhz*configging sdcache
> R5000/Rm5200 SCACHE
>
> Exception: <vector=ECC>
> Status register: 0x20000004<CU1,IPL=8,MODE=KERNEL>
> Error EPC: 0x802dc2c8
> CacheErr 0xe5000008<ER,EC,ED,EE,EI,SIDX=0x8,PIDX=0x0>
> --> ECC/Parity ERROR on the SysAD bus
> CRASH calling ecc_error_decode

- R5000 L2 cache is peculiar.  It's virtual address indexed, not the same as
R4000 nor RM527x/RM7000.

- I guess L2 cache is not properly initialized before use.  Then processor
gets confused and posts cache error exception (SIDX/PIDX value may
help).   Please comb through SMC-Sierra Knowledge Base.  I thought
there was a clue around there.

Toru Nishimura/ALKYL Techlogy