Subject: Re: latest O2 diffs
To: Toru Nishimura <email@example.com>
From: Rafal Boni <firstname.lastname@example.org>
Date: 12/09/2002 21:58:18
In message <000601c29ff1$2edd8780$0d00a8c0@paq5>, you write:
-> "Rafal Boni" <email@example.com> replied;
-> > Maybe I'm missing something, but I think the above snippet says that the
-> > secondary cache *is* actually physically indexed as described in the PMC
-> > Rm52xx docs.
-> It's my surprise R5000 doco insists itself virtual address index. I spent a
-> while to figure out how the L2 SRAM was drived looking at chip wiring.
-> No definite clue from it. (From designers' point of view, VA indexed
-> L2 is very questionable...)
Well, as I said, it seems to contradict itself (saying virutally indexed in
one place, but then describing the operations themselves as taking the phys.
address bits for the index), so I'm not sure how trustworthy either of the
descriptions actually is 8-)
I do agree with you that virtually indexed L2 does seem a questionable way
to design things...
-> I stepped across a KB item which mentions to cache error exception which
-> mandates L2 initialization. It's not about R5000, but may help.
Hmm, in the PMC (why do I keep wanting to say "QED"? 8-) KB? I've got the
Rm52xx KB somewhere, so I'll take a look through it...
Rafal Boni firstname.lastname@example.org
We are all worms. But I do believe I am a glowworm. -- Winston Churchill