In message <20010729.230840.32152264.he@uninett.no>, you write: 

-> Hi,
-> 
-> I'm currently running 1.5X from yesterday on my new Indigo2, and it's
-> been doing "make build" most of today.
-> 
-> A couple of oddities I note in the startup:
-> 
->   IOC rev 0, machine Indigo2 (Fullhouse), board rev 8
->   Timer calibration, got 1250000 cycles (1250000, 1250000, 1250000)
->   CPU clock speed = 125.00Mhz
-> 
-> Actually, it's 250MHz...

This is basically debug output and can be safely ignored, or maybe should
be removed/changed... The MIPS R4x00 have an odd clocking such that the 
cycle counter actually counts at half-speed, and this is just the results
of the cycle-counter calibration.  My 150Mhz box returns 75, the 133Mhz
Indy says 66.5, etc.

->   cpu0 at mainbus0: MIPS R4400 CPU (0x460) Rev. 6.0 with MIPS R4010 FPC Rev.
->  0.0
->   cpu0: L1 cache: 16KB/16B instruction, 16KB/16B data, direct mapped
->   cpu0: L2 cache: 1024KB/128B mixed, no snooping
->   cpu0: disabling IP22 SysAD L2 cache
-> 
-> The L2 cache is actually 2MB.  The disabling is because the cache code
-> isn't quite there yet, right?

The cache size is currently hardcoded to 1MB for the Fullhouse; the SysAD
cache it's disabling is the R4600/R5000 cache which there isn't any code
to drive yet.  So you should probably change the hardcoded 1MB to 2MB.

-> Finally, the build stopped at:
-> 
->   dependall ===> regress/lib/csu/initfini
[...]
-> I don't quite know how to deal with that...  Hints appreciated.

I haven't tripped over this one yet, and my SGIs are packed away in the
closet as we're re-flooring the computer room this week.  Sorry!

--rafal

----
Rafal Boni                                              rafal.boni@eDial.com
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