Subject: Re: Pegasos port status
To: Frank Wille <frank@phoenix.owl.de>
From: =?ISO-8859-1?Q?Jorge_Acereda_Maci=E1?= <jacereda@gmail.com>
List: port-powerpc
Date: 07/19/2006 22:25:44
Frank Wille wrote:
> Jorge Acereda MaciÓ wrote:
> 
> 
>>Ok, I've checked out a current tree and applied some of the 2.0 patches 
> 
> 
> I did that too, but my Pegasos hangs without doing any output.
> 
> 
> 
>>total memory = 256 MB
>>avail memory = 234 MB
>>bootpath /ethernet/port1@0,0
>>cbootpath /ethernet
>>mainbus0 (root): bplan,Pegasos2
>>cpu0 at mainbus0 (PowerPC,750CXE): 750 (Revision 3.1), ID 0 (primary)
>>cpu0: HID0 8090c0ac<EMCP,DOZE,DPM,ICE,DCE,SGE,BTIC,ABE,BHT>
>>cpu0: 56.26 MHz L2 cache present but not enabled
> 
> 
> The clock is wrong. You forgot to apply my changes from ofppc/clock.c? :)

I only applied the minimum set of patches to get it going. That one is 
just a problem with initialization order. The delay() function is taking 
the default value for ns_per_tick (320). The simplest thing I've come up 
with is this patch. cpu_initclocks() will be called twice, but it seems 
safe.


Index: cpu_subr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/powerpc/oea/cpu_subr.c,v
retrieving revision 1.26
diff -u -r1.26 cpu_subr.c
--- cpu_subr.c	24 Dec 2005 20:07:28 -0000	1.26
+++ cpu_subr.c	19 Jul 2006 20:23:48 -0000
@@ -481,6 +481,7 @@
  	aprint_normal("%s: HID0 %s\n", self->dv_xname, hidbuf);

  	ci->ci_khz = 0;
+	cpu_initclocks();

  	/*
  	 * Display speed and cache configuration.