Subject: Re: Pegasos port freezes at uvm_km_alloc1
To: port-powerpc <port-powerpc@NetBSD.org>
From: Matt Thomas <email@example.com>
Date: 12/08/2004 09:12:19
On Dec 8, 2004, at 8:55 AM, Frank Wille wrote:
> Matt Thomas wrote:
>>>>> Status: I get the copyright-message on screen, UVM is initialized,
>>>>> but the system freezes at the end of uvm_km_alloc1(), while trying
>>>>> to clear the first page of kernel memory with memset().
>>>> Are the L1/L2/L3 caches enabled?
>>> I think they're not. Should I enable the L2 caches before
> I don't think this is required, but I tried to enable L2 (512K)
> at the end of initppc() now. No effect.
>>> BTW, where are the L1 caches enabled? I didn't find it in the source.
>>> It's a 750CXe system, so L3 caches will be no problem.
>> L1 is usually tuned on in locore before you transfer control to
> L1 was already turned on by OFW as it seems (I'm not doing it
> in locore). I have inserted some debugging output in initppc():
> before oea_init(): HID0=0x8090c28c, MSR=0x00000000
> after oea_init(): HID0=0x8090c28c, MSR=0x00001032
> MMU is enabled, caches are enabled (even L2). Everything looks ok.
>>>> What bats are you initializing?
>>> oea_batinit(0) should setup a but for the first 256M of RAM. Nothing
>>> else... I think.
>> That's your problem. oea_batinit should only get I/O bats. It'll init
>> the BATs needed to address physical RAM (including 0) by itself.
> Now oea_batinit() got the following:
> This maps PCI-I/O and PCI-memory space. Maybe I should also map
> ISA-space at 0xfe000000, but there are only four BAT registers.
The kernel will "page" between BATs so that even though there are
only 4, you can address as much memory as you need with them.
> Anyway, it doesn't help. Still freezes when accessing 0x60001000
> (KERNEL_SRs are 6,7).
You should be at getting a DSI fault. What's your stack like before
accessing that location?