Subject: Re: ev64260 PCI location / boot monitor
To: Doug Fraser <firstname.lastname@example.org>
From: Matt Thomas <email@example.com>
Date: 04/13/2004 16:44:50
At 06:17 AM 4/13/2004, Doug Fraser wrote:
>When the boot monitor runs (PMON) it configures the
>PCI busses on the Discovery bridge. They were set to
>address space 0xC0000000, 0xD0000000, and IO space 0xE0000000.
because pmon is stupid. Unless you are have video cards, 256MB
per PCI is overkill. Don't forget the CSn regions.
>That caused a conflict which I could address by adding definitions
>to the config for USER_SR, KERNEL_SR and KERNEL2_SR.
>I changed the monitor to locate the PCI space at 4, 5, and 6
>so that the default USER, KERNEL, KERNEL2 spaces (12, 13, 14)
>would then work. We will have a maximum of 1GB of SDRAM, so
>that requires battable space for 0, 1, 2, and 3. Now that I am
>no longer setting my own USER (etc.) space, I could shove the
>PCI up at 9, 10, and 11.
You can do better.
>Is there information available for the powerpc port that discusses
>recomended IO and memory mapping locations for devices?
>Obviously having SDRAM at 0 and FLASH way up at 0xfff00000
>works fine, but I am looking for guidance on where the other
>non-PCI bus devices should be located. My first impulse is to
>stick them all in BAT 15 (along with the flash and the Discovery).
Shove everything as high as you can go. 1MB for the Discovery, 64MB
for each PCI, xx MB for each of the CS (including BootCS) should easily
fit in 256MB. That means you can use DBAT 1 to map those permanently.
Remember to sort so that the largest region(s) are at the lowest address
so that you automagic power-of-2 alignment.
Matt Thomas email: firstname.lastname@example.org
3am Software Foundry www: http://3am-software.com/bio/matt/
Cupertino, CA disclaimer: I avow all knowledge of this message.