Subject: Re: pmap_syncicache question
To: Ramesh BN <firstname.lastname@example.org>
From: Nathan J. Williams <email@example.com>
Date: 09/23/2003 15:20:08
Ramesh BN <firstname.lastname@example.org> writes:
> pmap_syncicache() take in a "physical" address and tries to flush
> the data cache and invalidate the instruction cache using the
> instructions "dcbst" and "icbi".
> The description of "dcbst" says it needs a EA, and translation and
> protection will be checked. How is this supposed to work if we use a
> "pa" instead of a "va"
If you're looking at src/sys/arch/powerpc/powerpc/pmap_subr.c, look at
the MFMSR()/MTMSR() around the use of dcbst anbd icbi; the MMU is
disabled while those instructions are used, so the addresses are not