Hi,

> Okay, I now have code that can enable the L3 cache on a 745x-class CPU.
> This works similarly to the existing L2CR_CONFIG option that can be added to
> a kernel config.  Lacking much imagination, I called the new option
> L3CR_CONFIG.

Excellent!

> The changes consist of some new code in cpu_config_l2cr() in
> arch/powerpc/oea/cpu_subr.c, a bunch of L3CR definitions to
> arch/powerpc/include/spr.h, and the addition of L3CR_CONFIG alongside
> L2CR_CONFIG in arch/powerpc/conf/files.powerpc.  The patches are available
> at:
> http://users.easystreet.com/monroe/l3setup.patch

Ha ha ha ha... I think we were both onto the same thing... I copied and
pasted all of the L2CR values and started filling in the stuff from the
Motorola PDF, but you're way ahead of me. Thank you!

> The system I've seen this work on is a Power Macintosh 7500 with one of
> these:
> http://sonnettech.com/product/crescendo_pci.html
> Specifically the 700MHz G4 model.

That's the same one I have.

> The options I added to my kernel config are:
>
> # Sonnet Crescendo/PCI G4/700 cache setup
> options L2CR_CONFIG="(L2CR_L2E)"
> options L3CR_CONFIG="(L3CLK_40|L3CKSP_4|L3PSP_0|L3RT_PB2_SRAM)"
>
> which corresponds to a 1M L3 cache running at a 4:1 ratio.  (For the record,
> this was derived by booting the machine under Mac OS X, installing the
> Sonnet software and capturing a value of 0x8f020300 from L3CR.)  According
> to the marketing specs on the upgrade, the cache should run at 200MHz (or
> 3.5:1), but I haven't tried that yet.

I'll give that a try.

> Could someone please review this patch?  If it passes inspection, what do I
> need to do to get it committed?

I'll try out this patch, commit it if everything looks good, and ask
people with new G4s with 745x to test it to make sure we didn't break any
other systems (although I doubt it, since this doesn't get used unless
explicitely put in).

Anyone care to test this on a newer G4?

Thanks,
John Klos