Subject: Variable cache sizes
To: None <>
From: None <>
List: port-powerpc
Date: 02/17/2002 23:02:56
We need a much more flexible method to handle different 
cache and cache line sizes on PPC machines.  The IBM
PowerPC 4xx series comes in a variety of different cache
sizes and cache line sizes.  Some models have no data or
instruction cache at all, which will cause cache 
manipulation instructions to fault.  Since the same CPU
core can be packaged in a number of different ways, this
information must be determined at run-time.

I plan to add:

struct cache_info {
	int dcache_size;
	int dcache_line_size;
	int icache_size;
	int icache_line_size;

to the cpu_info structure.  This is filled in by the
machine-dependent `cpu_probe_cache(void)' routine that
is called from inside cpu_attach().

In addition, the port needs to provide a set of cache 
flush routines which make use of this data structure:

void dcache_flush_page(vaddr_t);
void icache_flush_page(vaddr_t);
void dcache_flush(vaddr_t, vsize_t);
void icache_flush(vaddr_t, vsize_t);

These routines allow pmap to be separable from the
details of that specific processor implementation.

Finally, the kernel memcpy()/memset() routines will
access this information rather than a compile-time