Subject: Re: bzero.S and assym.h (Re: CVS commit: syssrc/sys/lib/libkern/arch/powerpc)
To: None <email@example.com, firstname.lastname@example.org>
From: None <email@example.com>
Date: 12/06/2001 21:19:20
| Frank van der Linden wrote:
| > Eduardo and I are working on a port to a chip based on an older
| > 40x core (the 401D2). This one has a cache line size of 16.
| I'm fully aware of the 16 byte cache line size of the 40x processors
| (apart from the 405). That's the reason I introduced the CACHELINESIZE
| sysctl in the first place (while doing a port to the IBM Network Station
| which I hope to integrate into our tree once I can find enough time to
| clean it up).
| However, are you really planning to run the same kernel on one of those
| and on, say, a PowerMac?
No, but I am planning on running the same kernel on say a 401 with a
16-byte cache line and a 405 with a 32-byte cache line.