Subject: Re: bzero.S and assym.h (Re: CVS commit: syssrc/sys/lib/libkern/arch/powerpc)
To: Wolfgang Solfrank <email@example.com>
From: Frank van der Linden <firstname.lastname@example.org>
Date: 12/05/2001 02:17:11
On Tue, Dec 04, 2001 at 02:45:38PM +0100, Wolfgang Solfrank wrote:
> Huh? Would you care to explain on what embedded PPC CPUs we do run
> currently? The only one I can see in our tree is the 405GP which
> does have the same cache line size as the other PPC CPUs we support,
> namely 32. And that one even needs a different kernel anyway.
Eduardo and I are working on a port to a chip based on an older
40x core (the 401D2). This one has a cache line size of 16.
What's worse, it has a known error that forces the kernel to mark
some parts of memory write-through. In which case the dcbz instruction
will trap. So for this case, using dcbz in the kernel is not a good
idea; checking if this is cacheable memory for each call is way
too slow, and fixing up the error in the trap handler would be
So, you need to check what the cacheline size is, and whether you
can safely use dcbz at all time. This would mean 2 sysctl calls
for userspace (or one sysarch cachectl query call getting some flags),
and for the kernel that's 2 #defines at least, but quite possibly
one of them should be a variable.
Frank van der Linden email@example.com
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