Subject: Re: bzero.S and assym.h (Re: CVS commit: syssrc/sys/lib/libkern/arch/powerpc)
To: David Edelsohn <>
From: Greg Lehey <>
List: port-powerpc
Date: 12/04/2001 12:16:11
On Monday,  3 December 2001 at 20:44:30 -0500, David Edelsohn wrote:
>>>>>> Greg Lehey writes:
> Greg> In general the 60x range has 32 bytes cache lines, embedded processors
> Greg> (40x and 80x) have 16 bytes, and the 64 bit processors have 128 byte
> Greg> cache lines.  There are exceptions, like the 405, which is a 64 bit
> Greg> embedded processor and has 32 byte cache lines.
> 	The PPC405 is a 32-bit embedded processor.

I stand corrected.  I had been told that it was 64 bits, but didn't
check.  Am I correct about the cache line size?

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