Re: data and instruction caches

[David Edelsohn <dje%watson.ibm.com@localhost>]

>>>>> Emmanuel Dreyfus writes:

Emmanuel> Questions: is isync to flush instruction cache and sync to flush
Emmanuel> processor cache?

Emmanuel> Anyway, we flush a cache (instruction or data, I don't know), then we
Emmanuel> copy. Where do we flush the data cache to ensure that when we branch, 
we
Emmanuel> does not jump to a location where code has not been flushed yet from 
the
Emmanuel> data cache?

Emmanuel> There must be some sync/isync after exitting sendsig(), but I don't
Emmanuel> really understand how it works when we get out of sendsig and before 
we
Emmanuel> enter the signal trampoline on the stack. If someone can explain me...

The suggested sequence for 604 and 604-derived processors is:

     dcbst (or dcbf)          ;# flush data block to memory
     sync                     ;# ensure flush made it to memory
     icbi                     ;# invalidate block from icache
     sync                     ;# wait for icbi to be globally performed
     isync                    ;# refetch instructions

        The isync really is saying don't speculatively decode or execute
instructions past the synchronization point.

David