pmap_zero_page(): dcbz alignment exception

[Tad Hunt <tad%entrisphere.com@localhost>]

We're in the process of porting NetBSD to the MPC8260.  Our platform
is the MPC8260ADS evaluation board.  We've got an ethernet driver,
and a serial port driver, and we're actually running user processes. (Whoo!)

My first question has to do with the dcbz instruction in
arch/powerpc/powerpc/pmap.c:pmap_zero_page().

>From "The PowerPC Microprocessor Family, The Programming Environments"
manual, section 5.1.5.1.2 (pp 5-9):

        The dcbz instruction clears a single cache block as follows:

        ...

        o If the target is designated as either caching-inhibited
          or write-through, then either all bytes in main memory
          that correspond to the addressed cache block are cleared,
          or the alignment exception handler is invoked.  The
          exception handler should clear all the bytes in main
          memory that correspond to the addressed cache block.

        ...

This dcbz instruction causes an alignment exception on the MPC8260.
I assume that this is not the case on the other PowerPC ports, otherwise
the bzero() call in pmap_zero_page() wouldn't have been "#if 0"'d out.

To get things working, I changed the #if 0 to a #if 1, but I would rather
not make any changes in the portable code (if possible).

Do the other ports run with the cache in write-back mode rather than
write through (thus avoiding this exception), or do they not raise
the exception (and clear main memory instead)?

Obviously, I could write the exception handler, but I think it'll be
more efficient to avoid the dcbz by calling bzero(), rather than trying
to recover from it failing.

-Tad