Subject: Re: TRAP CALL IN CASE OF POWERPC
From: Ignatios Souvatzis <firstname.lastname@example.org>
Date: 08/19/2000 11:22:08
On Sat, Aug 19, 2000 at 11:16:58AM +0530, karan khanna wrote:
> David Edelsohn wrote:
> > >>>>> karan khanna writes:
> > karan> Can any body tell me how various TRAP calls ,which were implemented
> > karan> earlier in previous versions of
> > karan> Motorolla micro processors viz-68k family, can be implemented in case of
> > karan> POWERPC.
> > karan> There were many trap vectors provided in case of 68K family but in PPC
> > karan> only one
> > karan> unconditional trap is available. How can rest unconditional traps be
> > karan> implemented.
> > Pass a parameter in a register recognized by the trap handler if
> > the trap was caused by a trap instruction?
> > David
> This could be true if we could have the flexibility to pass a parameter but when I
> want to use trap as a breakpoint instruction i.e replace the instruction by a
> simple trap call and also for similar more purposes. Is there any possible way
Depends on what you want to do.
The PPC do only have one sc (System Call) instruction, but you could
check in the sc routine where you come from...
If you only want to watch one address, at least on the PPC 603 and 604,
there is the Instruction Address Breakpoint Register. You set this to the
instruction address you want to watch, and set a enable flag, and get
signaled via the breakpoint exception.
There's also a trace exception, callable either from each instruction completion
or from branching.
If you really want to use multiple sort-of different trap instructions,
you could abuse illegal instructions (e.g., 64bit instructions on 32bit
cpus); but you'll get a program exception for all of them, and the program
exception handler will have to distinguish in software.
I really suspect you want to download the PPC603/MPC603 or PPC604/MPC604
"UM/AD" pdf document and read a bit. You'll probably need the "32 bit program
environment manual" pdf, too.