Subject: Re: TRAP CALL
To: Ignatios Souvatzis <is@jocelyn.rhein.de>
From: karan khanna <karan@cdotd.ernet.in>
List: port-powerpc
Date: 05/11/2000 09:26:15
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Ignatios Souvatzis wrote:
> On Tue, May 09, 2000 at 02:06:41PM +0530, karan khanna wrote:
> > Can any body tell me how various TRAP calls ,which were implemented
> > earlier in previous versions of Motorolla micro processors viz-68k
> > family, can be implemented in case of POWERPC.
> > I can provide specific data if any body interested.
>
> Uhm, I'm not sure what exactly you want...
>
> most of the situations leading to traps on m68k create some exception on
> the PowerPC cpus. Read the PPC Programming Environments Manual for details,
> or the particular CPUs User's manual, for details. They are available as
> PDF documents from Motorola's WWW site (http://www.mot.com/)
>
> Regards,
Thanks for the reply ... I can make the problem clear to you... In case of
m68k there
are more than one trap calls
implemeted which on calling lead to different vectors and so can have
different
handling but in case of POWERPC (
particularly specifing M8260) has only one TRAP which is genrated according to
special conditions viz illegal instruction
or priviledge instruction or any condition in trap instruction is met--the
exception
is 007. But if I want to implement
another trap call which can index into different vector how can that be
possible. If
you have any idea please reply.
thanks
karan
--
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The tough get going.
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Ignatios Souvatzis wrote:
<blockquote TYPE=CITE>On Tue, May 09, 2000 at 02:06:41PM +0530, karan khanna
wrote:
<br>> Can any body tell me how various TRAP calls ,which were implemented
<br>> earlier in previous versions of Motorolla micro processors viz-68k
<br>> family, can be implemented in case of POWERPC.
<br>> I can provide specific data if any body interested.
<p>Uhm, I'm not sure what exactly you want...
<p>most of the situations leading to traps on m68k create some exception
on
<br>the PowerPC cpus. Read the PPC Programming Environments Manual for
details,
<br>or the particular CPUs User's manual, for details. They are available
as
<br>PDF documents from Motorola's WWW site (<a href="http://www.mot.com/">http://www.mot.com/</a>)
<p>Regards,</blockquote>
Thanks for the reply ... I can make the problem clear to you... In case
of m68k there
<br>are more than one trap calls
<br>implemeted which on calling lead to different vectors and so can have
different
<br>handling but in case of POWERPC (
<br>particularly specifing M8260) has only one TRAP which is genrated according
to
<br>special conditions viz illegal instruction
<br>or priviledge instruction or any condition in trap instruction is met--the
exception
<br>is 007. But if I want to implement
<br>another trap call which can index into different vector how can that
be possible. If
<br>you have any idea please reply.
<p>thanks
<br>karan
<pre>--
***************************************************************************
When the going gets tough...
The tough get going.
***************************************************************************</pre>
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