Jason Thorpe wrote:
> To quote "PowerPC Microprocessor Common Hardware Reference Platform: A
> System Architecture", section 12.2.1 - SMP-Safe Boot:

 Oh, you have that book, too?  I can't remember where I got it, maybe from
the OFW "training" i had last year in Phoenix.

 This book explains the CHRP Architectures in detail and was published by
Motorola, IBM and Apple.

 I cite the book's first page for those among this group who might be
interested:

 "To order copies of this book, please contact the publisher or your Apple,
IBM, or Motorola contacts listed in 'Source for Documents'." 
(Ha, great! :-)

 The ISBN-Number is 1-55860-394-8.  "PowerPC Microprocessor Common Hardware
Reference Platform:  A System Architecture"

 You can get the postscript version of the book here:

 ftp://ftp.austin.ibm.com/pub/technology/spec/

 (Valuable source!)

> 3. One of the first things that the firmware 

 Note the "firmware" here.

> does is establish one of
> the processors as the `master'. The `master' is a single processor which
> continues with the rest of the booting process; all of the others are
> places in a `stopped state'.  A processor in this `stopped state' is out
> of the picture; it does nothing that affects the state of the system and
> will continue to be in that state until awakened by some outside force
> such as an inter-processor interrupt (IPI).

 My understanding is:  OFW does all for us, and we don't have to care about
unless we want SMP?

-- 
Markus Illenseer