Subject: Re: MIPS cache rototill progressing!
To: None <>
From: None <>
List: port-pmax
Date: 07/13/2001 20:52:21 writes:
> The great uncertainness clouding over my head for long time is how
> cache machinary works when the target virtual address range is subject
> to TLB miss.  ASiD/G is fine.  They would work as designed.
> Apparently there are cautions, limitations and pitfalls around the case
> cache insn encounters TLB miss.  Can anybody out there provide definitive
> explanations about it?

if you're feed a VA into a cache op, the CPU is allowed to attempt to
translate that VA into a PA.  If it does so and that VA->PA
translation isn't described by some valid mapping (e.g. kseg0/kseg1,
or a valid TLB entry), you'll take a fault.

if you're doing the cache op on a VA with the current context, then
you'll be OK but you may get a fault -- you need to be sure to do the
cache ops _before_ doing whatever you do to prevent your TLB miss
handler from processing the miss.  (i.e., if you use a page table or
whatever, which is consulted by the TLB miss handler, don't remove the
valid entry from the page table before you do the cache ops, else your
TLB handler may be Unhappy if you _do_ get a miss.)

If you're doing the cache op on a VA not in the current context, then
it may be best to just punt and do the index ops.  probably depends on
how hard it is for you to switch VM contexts.  8-)