On Tue, 27 Mar 2001, John Maier wrote:

> After some more consideration, I'm guessing that the main board was only
> 32bit.
> The reason I think this is; the memory is 40bit (32bit data + 8bit
> ECC/parity).
> Since all subsequent R4400s can run in a 32bit mode and are 64bit
> multiplexed
> 32bit bus, this would work okay.  Also there an 8-bit bus containing check
> bits
> for the SysAD bus on the R4x00, which if it exists on the R3000, may explain
> how the extra 8 bits of memory are used.

 Note that the ECC logic is incorporated into the MT ASIC, so the
treatment of specific bits of the memory really depends on a specific
daughterboard (and may differ between KN03 and KN05!). 

> If DEC had put the chip into 64bit mode, this would have resulted in a 2nd
> strobe of
> the address and data lines on a 32bit bus and would also require the binary
> data to
> be 64bit aligned, which would have made an OS MIPS II instruction
> incompatable.

 You only need to dword-align 64-bit data.  You only access 64-bit
quantities with 64-bit data transfers, such as these performed by "ld" and
"sd"  instructions.  But if you use these instructions you already know
you need to align data appropriately. 

> Also it is highly unusual to maintain multiplexed 64bit through out a
> system.
> Typically you de-multiplexed the bus then access the hardware with the full
> core channel.

 Alternatively you may just drive low 32 bits of data when accessing
peripheral devices with high 32 bits going into oblivion upon writes and
left floating (or hardwired) upon read.  You may even "forbid by specs" 
64-bit accesses to non-memory addresses -- only the kernel is allowed to
access them normally, so that's not a big problem.

 32-bit programs run just fine unmodified on 64-bit MIPS CPUs.  Even the
virtual address map is compatible.  Given most memory accesses are burst
cache line fills/writebacks the gain from accessing main memory in 64-bit
quantities is considerable.  I'm sure DEC engineers must have taken it
into account when designing the system.

-- 
+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+--------------------------------------------------------------+
+        e-mail: macro@ds2.pg.gda.pl, PGP key available        +