>  The MB ASIC is a 40/25 MHz (CPU/system) domain separator (basically a
> FIFO).  Apart from the CPU and the cache, it's the only chip that is 40
> MHz driven.  The 40 MHz clock generator is integral to the daughterboard.
>
>  The MT ASIC is a memory controller (with all usual functions except from
> driving RAS and CAS lines, which is performed by the onboard MS ASIC) as
> well as a bridge between the CPU, TURBOchannel and memory.

That helps.

> > > 2) The R3000 is a time multiplex 32-bit bus chip, the PGA R4400 was
packaged
> > > as 64bit bus, so is the bus going to the main board a 32 or 64bit
path?
<snip>
>  No idea here, but since at the time /240 was being developed, an R4K
> daughterboard was already being considered the data path might either be
> 64-bit or 32-bit.  Given the memory controller is on the daughterboard it
> really depends on how data lines are routed between the daughterboard and
> memory modules.

After some more consideration, I'm guessing that the main board was only
32bit.
The reason I think this is; the memory is 40bit (32bit data + 8bit
ECC/parity).
Since all subsequent R4400s can run in a 32bit mode and are 64bit
multiplexed
32bit bus, this would work okay.  Also there an 8-bit bus containing check
bits
for the SysAD bus on the R4x00, which if it exists on the R3000, may explain
how the extra 8 bits of memory are used.

Also, after reading some of the specs on MIPS's page, the virtual address is
either 32-bits or 64 bits wide making the R4400 a true 64-bit processor. In
32-bit address mode, the user virtual address space is 2 GB while in 64-bit
mode the virtual address space is 1 TeraByte.

If DEC had put the chip into 64bit mode, this would have resulted in a 2nd
strobe of
the address and data lines on a 32bit bus and would also require the binary
data to
be 64bit aligned, which would have made an OS MIPS II instruction
incompatable.
Also it is highly unusual to maintain multiplexed 64bit through out a
system.
Typically you de-multiplexed the bus then access the hardware with the full
core channel.

> > > 3) Does the SG-615P chip, on the daughter card, control the CPU
frequency?
> > > If so, does it also generate the clock for the main board?
<snip>
>  No -- the board uses an own clock generator.  The CPU clock is not
> available outside the daughterboard.

Now I see it, there a 20Mhz freq chip on the daughter card (2x to give
40Mhz) and a 50Mhz
freq chip on the main board (/2 to give 25Mhz).

Cool stuff!!!

jam