Subject: Re: MIPS Asym. for MAXINE Access Bus
To: None <port-pmax@netbsd.org>
From: Toru Nishimura <nisimura@itc.aist-nara.ac.jp>
List: port-pmax
Date: 12/12/2000 11:29:05
> NetBSD/pmax could not find out a sane solution to cope with the design
> inconsistency so far, and does overblocking.
One more. I'm planning to make cpu_intr() and trap() called in such a
condition that IE bit of processor SR is left turned on. This should
(I was told so) improve clock drifting on high load. Overblocking is
a bit general issue across MIPS ports.
Tohru Nishimura