On Thu, 18 May 2000, emanuel stiebler wrote:

> From: Toru Nishimura <nisimura@itc.aist-nara.ac.jp>
> 
> 
> > How (un)realistic is it to build the handsomely neat (the twice large
> > of business card) CPU daughter board hooking 50MHz IDT R3081E.  PMON
> > source code has initilization sequence examples of the chip.

Why just 50, why not a nice 133 or so especially if there are MIPS
processors that have a high clock multiplier...

> 
> If (or a BIG IF) that should make sense, take a RM5231 for it. So you could
> run nearly the same design (but still different boards) for the 5000/1xx &
> 5000/2xx workstations.
> 
> realistic ? YES.
> 
> Who would like to have one ?
> 
> That's the problem. I asked the same question, probably 1-2 years ago, and
> nobody was interested :-(

	If someone does the design, I will do the PCB layout and make a
few cards (assuming I can do it in 6 layers) (I think the DEC card is 8 or
more layers, but most layers look pretty empty)

	I still think using the old ASIC with a newer CPU is a
possibility, with maybe the addition of some wait state logic to slow
access to the ASIC. The MIPS bus to ASIC connections can be determined
with an Ohmeter, same as the ASIC - Honda connector...

> 
> cheers,
> emanuel
> 
> 
> 
> 
> 

Peter Wallace
Mesa Electronics