Subject: Re: LSI Logic
To: None <>
From: Toru Nishimura <>
List: port-pmax
Date: 05/18/2000 10:57:39
>> Its actually a good design, all high speed local signals confined to the
>> daughter-card, once the signals get on the main card, you probably have
>> much longer signal lengths. 
>   So reverse engineering the ASIC isn't really necessary.  All that needs to be
> done is fiure out the daughterboard/motherboard protocol and build a new ASIC
> for the CPU of interest. :)

How (un)realistic is it to build the handsomely neat (the twice large
of business card) CPU daughter board hooking 50MHz IDT R3081E.  PMON
source code has initilization sequence examples of the chip. 

Tohru Nishimura