Hi, 

I've got a question regarding interrupt handling of the mc146818 clock
during the netbsd boot sequence.  I'm working on a DEC3100 simulator
and trying to get Netbsd to run on it, but I'm running into problems at
this juncture.  

For starters, I'm looking in the file: mips_mcclock.c and trying to figure
out what its doing.

From the comments, it looks like interrupts are blocked.  (i.e.  the IEc
bit of the status register is set to 0).  Then periodic interrupts are
enabled on the mc146818 by setting some of its control registers which are
located in memory.  It looks like 'rega' holds the frequency of
interrupts, 'regb' the info for enabling interrupts, and 'regc' the info
for pending interrupts. 

I'm assuming that the clock interrupts still set the hardware interrupt
fields of the Cause Reg.

Based on this understanding, I've got the following questions:
1)  Does the hardware always need to go to memory and check these clock
registers every cycle (in addition to checking the Status Reg)?

2)  Once an interrupt occurs, what changes the 'regb' register to disable
interrupts so that the exception can be processed?  (i.e.  should the
exception processing hardware be changing the regb register similar to
what it does for the Status Register.)  Similarly, would the rfe
instruction have to restore the state of these control registers?

3)  Finally, just want to make sure:  Does the processor still branch to
the General Exception vector for this exception?


Regards,

Binson Wei