On Wed, 20 May 1998 09:30:32 +0900 (JST) 
 nisimura@is.aist-nara.ac.jp (Toru Nishimura) wrote:

 > >>   UVM stable?  How about when it even runs?  [I can boot it, but as soon
 > >> as it runs out of free memory and the page daemon starts to run, it hangs.
 > >> The page daemon seems to hang trying to do I/O.]
 > 
 > Um, I've heard differently.  I'll talk with the guy who's making a
 > progress with his machine.

Now that the pmap bug that kept it from running at all is fixed (nice
hunting Tsubai and Michael!), I am planning on running it on my DECstations
to see how well it works...  I'm just really surprised that it's that
unstable on the MIPS.

Perhaps the reason it "hangs" when the pagedaemon becomes active is because
the MIPS pmap doesn't do referenced/modified tracking?  (Although, if that
were the case, it would certainly be unfortunate if UVM couldn't cope with
that...)

 > > I suspect these problems are due to bugs in the MIPS pmap, or other
 > > MIPS-specific code.
 > >
 > > Someone really ought to port the NetBSD/alpha pmap to the MIPS... :-)
 > 
 > This sounds very interesting.  What's the benefit we can expect for
 > MIPS?  I've a little information other than overcoming "maxusers woe."

It mostly manages memory better, and is significantly cleaner.  You
certainly get rid of the "maxusers" problem you're referring to, and
something that's easier to read and follow (LOTS of comments, LOTS of
optional sanity checking code).  I've also put a lot of thought into
multi-processor support, and have been adding the necessary fine-grain
locking to the Alpha pmap.  There's also support for emulating modified
and reference bits, which the Alpha also lacks (although the Alpha
has the Fault-On-{Execute,Read,Write} PTE bits that help with that).
You certainly could modify that code to work on the MIPS (make use
of those software-use TLB entry bits! :-)

The Alpha pmap is also well-tested with UVM, and supports UVM's new
PMAP_NEW interface.

Hardware-wise, the MIPS and Alpha MMUs are quite similar - pure TLBs.
Both are software-load.  The only real difference is that the Alpha's
OSF/1 PALcode does the TLB-load-on-miss.  The PALcode uses a 3-level
table-walk, much like the M68040 (there is some evil in there related
to the Virtual Page Table, and VPT TLB entries for fast TLB-load, but
you don't need to worry about that for the MIPS :-)

Both also tag TLB entries with Address Space Numbers (TLBPIDs in MIPS
terminology).

Both also have direct-mapped kernel segments (KSEG) which is quite
useful for accessing page tables, etc.

Your TLB miss trap handler takes the place of the PALcode doing the
table walk... compound tests to simulate FOx... you're mostly there.

Jason R. Thorpe                                       thorpej@nas.nasa.gov
NASA Ames Research Center                            Home: +1 408 866 1912
NAS: M/S 258-5                                       Work: +1 650 604 0935
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