One might ask `why', but..

>    Due to lack of documentation, I've been looking through the
>NetBSD/pmax (1.2BETA) source for pointers on how to set stuff up.  As far
>as I can tell, I'm setting up all the Zilog SCC (8530) registers properly.
>I was wondering if there is something special I need to do with the ASIC
>to allow the interrupts through.

Yes, there is...

> and if so, if someone could point me to
>where exactly to look for that?

...  see ioasic.h.  If memory serves, the interrupt bits are enabled
by writing to the corresponding notification bits in the system
control register. Exactly which bits are mapped to which, and how
they're reported, is different on each model of ioasic Decstation.


>    Alternatively, does anyone know any online sites to get the
>documentation for the ASIC chip in the 5000/1xx series (KN02-BA)?  I
>can't seem to find it with altavista.

According to well-placed sources, there is no such documentation
publically available.  The docs for the 2100/3100 (PMIN/PMAX) and
5000/200 (3MX) were released, but the equivalent specs for
ioasic-based machines (3MIN, MAXINE, 3MAXPLUS, model number dependent
on CPU speed) were never released.