Jon Buller <jonb@metronet.com> writes:

  > Well, that total solution can only be described as YUCK!  Would it
  > be hard (or even possible) to allow the UART to toggle RTS when,
  > say 10 bytes were left in the buffer, and then have the interrupt
  > manually set RTS, and empty the fifo into the buffer, to accept 2
  > or 3 (or even 13 or 14) more chars from slow responders?  Then when
  > the buffer drops down to 20 or 30 bytes free, let the UART deal
  > with RTS again.

I don't think it is really possible. The problem is FIFO overruns,
not ring buffer overruns. The FIFO is only 4 bytes deep (8 in the
26C92) and the only way you can give an illusion of greater depth
is to take stuff out of the FIFO and stick it in a ring buffer.
Under software control you can set RTS when the ring buffer gets to
highwater, but that is not much help if it is the FIFO which is
overrunning.

The software control of RTS is not that bad. The z8530 code works that
way, but it is complicated by the chip uglyness. I think I could code
the software control pretty easilly so I might give it a go if only as
a "proof of concept".

Actually a few calculations imply that there *should* be no problem
with the scsi pseudo dma. It transfers in 512 byte blocks. That is
512us at 1 MB/s which is less than 2 characters time at 38.4 kB and
there is at least a 4 byte fifo.  However, there is no guarantee on
how long the 512 byte block transfer will take. Hopefully and sensible
scsi device with caches and the ability to disconnect and so on will
not go and do a seek in the middle of a block transfer, but as I say
there is no guarantee.

Ian