My CHRP / PReP support code

[Jochen Kunz <jkunz%unixag-kl.fh-kl.de@localhost>]

Hi.

Today I found some spare cycles to bring my old patches up to -current:

http://www.unixag-kl.fh-kl.de/~jkunz/NetBSD/ofppc/ofppc-3.99.16.tar.gz

This is no patch, it is my complete src/sys/arch/ofppc directory. The
changes are so big that it doesn't make much sense to deliver this as a
patch. Just run
cd src/sys/arch && mv ofppc ofppc.orig && tar zxf ~/ofppc-3.99.16.tar.gz
and you are done.

Note that this is nothing ready to use. It compiles and it should boot
and go through autoconf(9) on most CHRP and PReP machines with OpenPIC.
It is very much hacked. I am still experimenting how to lay things out
and how to design platform support. Expect major code changes when we
get a bit further with the interrupt stuff. (The firepower and motorola
directories are doomed to be removed and the stuff in the chrp directory
will be merged into the code in the ofppc/ofppc directory etc..)

Talking about interrupts: This is the bigest problem of this code at the
moment. The entire interrupt routing code doesn't work right. Clock
stuff seems to be somwhat broken too. Mostly because I don't understand
what all this stuff should do and how. These subsystems are not well
documented and it is quite hard for me to get the required knowlege by
reverse engineering other existing code.

Tim, or anyone else: It would be a really greate favor if you could look
at the interrupt stuff. Once we got that working I'll shape up the rest
and bring it to a state where I can commit it. My goal is to commit when
we got it running single user with a diskless NFS root.

Teaser:
NetBSD 3.99.16 (GENERIC-ofppc) #15: Wed Mar 15 23:25:32 CET 2006
        build@Zimbo:/usr/src.new/src/build/GENERIC-ofppc
total memory = 256 MB
avail memory = 241 MB
bootpath /pci@80000000/ethernet@c/netbsd.ofppc
cbootpath /pci@80000000/ethernet@c
mainbus0 (root): IBM,7043-150
cpu0 at mainbus0 (PowerPC,604e@0): 604ev (Revision 1.0), ID 0 (primary)
cpu0: HID0 c001c086<EMCP,DBP,NHR,ICE,DCE,SGE,BHT,NOPDST>
cpu0: 375.00 MHz
ofbus0 at mainbus0 (event-sources)
epow-events at ofbus0 not configured
memory-controller@fec00000 at mainbus0 not configured
ofbus1 at mainbus0 (rom@ff000000)
boot-rom@fff00000 at ofbus1 not configured
rtas at mainbus0 not configured
chrp0 at mainbus0 (pci@80000000)chrp_isa_init

pci0 at chrp0 bus 0
pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
pchb0 at pci0 dev 0 function 0
pchb0: Motorola MPC106 "Grackle" Host Bridge (rev. 0x40)
pcib0 at pci0 dev 11 function 0: 
pcib0: Symphony Labs 83C553 PCI-ISA Bridge (rev. 0x10)
slide0 at pci0 dev 11 function 1
slide0: Symphony Labs 82C105 IDE controller (rev. 0x05)
slide0: device disabled (at device)
Fixing AMD PCnetPCI Vendor ID.
pcn0 at pci0 dev 12 function 0: AMD PCnet-PCI Ethernet
pcn0: Am79c971 PCnet-FAST rev 5, Ethernet address 00:04:ac:31:1c:7f
pcn0: interrupting at irq 6
nsphy0 at pcn0 phy 1: DP83840 10/100 media interface, rev. 1
nsphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
ukphy0 at pcn0 phy 31: Generic IEEE 802.3u media interface
ukphy0: Am79C972 internal 10BASE-T interface (OUI 0x000058, model 0x0001), rev. 
1
ukphy0: 10baseT, 10baseT-FDX, auto
mpic0 at pci0 dev 13 function 0: IBM MPIC (rev. 0x00)
Symbios Logic 53c875/876 (SCSI mass storage, revision 0x04) at pci0 dev 16 
function 0 not configured
ppb0 at pci0 dev 23 function 0: IBM 82351 PCI-PCI Bridge (rev. 0x01)
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled, rd/line, wr/inv ok
isa0 at pcib0chrp_isa_attach_hook

com0 at isa0 port 0x3f8-0x3ff irq 4: ns16550a, working fifo
com0: console
com1 at isa0 port 0x2f8-0x2ff irq 3: ns16550a, working fifo
isapnp0 at isa0 port 0x279: ISA Plug 'n Play device support
isapnp0: read port 0x203
boot device: <unknown>
root device: 
use one of: pcn0 ddb halt reboot
root device: 

-- 


tschüß,
       Jochen

Homepage: http://www.unixag-kl.fh-kl.de/~jkunz/