Jeff Smith wrote:
> 
> This should be resolved with the lastest mips_machdep.c.  I will
> double check the flushing path you describe, it may only actually
> be needed on writeback cache machines.

It is interesting to note that the machine that won't boot is R4k based:


SONY NET WORK STATION, Model NWS-5000, Machine ID #15788
mainbus0 (root)
cpu0 at mainbus0: MIPS R4400 CPU (0x460) Rev. 6.0 with MIPS R4010 FPC
Rev. 0.0
cpu0: L1 cache: 16KB/16B instruction, 16KB/16B data, direct mapped
cpu0: L2 cache: 1024KB/64B mixed, no snooping
ap0 at mainbus0


It may be more than just a write-back cache issue.  The external L2
cache is
unified in which case you have to be careful about what order you touch
the 
I and D caches.    How does the L2 cache differ from the QED 5231
system?

Wayne
-- 
  _____	   	Wayne Knowles,  Systems Manager
 / o   \/   	National Institute of Water & Atmospheric Research Ltd
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