Anyone have any objections to me committing the following change, which
makes ddb's tlb command show 36-bit MIPS addresses by default (only for
MIPS3 ISAs).

For machines with only 32-bit paddrs it adds an extra zero.  (Although
the MIPS ISA specifically supports 36-bit phys addresses.)

I think that on 64-bit mips it will actually show a full a 64-bit
address, but it won't be neatly aligned if bigger than 36 bits. :-)  but
i think that is better than just arbitrarily chopping off the upper bits.

    -- Garrett

*** db_interface.c.~1.55.~    Sat Dec 24 12:07:19 2005
--- db_interface.c    Mon Feb 20 21:14:11 2006
***************
*** 49,54 ****
--- 49,55 ----
  #include <mips/mips_opcode.h>
  #include <dev/cons.h>
 
+ #include <machine/int_fmtio.h>
  #include <machine/db_machdep.h>
  #include <ddb/db_access.h>
  #ifndef KGDB
***************
*** 367,379 ****
              db_printf("TLB%c%2d Hi 0x%08x ",
              (tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*',
                  i, tlb.tlb_hi);
!             db_printf("Lo0=0x%08x %c%c attr %x ",
!                 (unsigned)mips_tlbpfn_to_paddr(tlb.tlb_lo0),
                  (tlb.tlb_lo0 & MIPS3_PG_D) ? 'D' : ' ',
                  (tlb.tlb_lo0 & MIPS3_PG_G) ? 'G' : ' ',
                  (tlb.tlb_lo0 >> 3) & 7);
!             db_printf("Lo1=0x%08x %c%c attr %x sz=%x\n",
!                 (unsigned)mips_tlbpfn_to_paddr(tlb.tlb_lo1),
                  (tlb.tlb_lo1 & MIPS3_PG_D) ? 'D' : ' ',
                  (tlb.tlb_lo1 & MIPS3_PG_G) ? 'G' : ' ',
                  (tlb.tlb_lo1 >> 3) & 7,
--- 368,380 ----
              db_printf("TLB%c%2d Hi 0x%08x ",
              (tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*',
                  i, tlb.tlb_hi);
!             db_printf("Lo0=0x%09" PRIx64 " %c%c attr %x ",
!                 (uint64_t)mips_tlbpfn_to_paddr(tlb.tlb_lo0),
                  (tlb.tlb_lo0 & MIPS3_PG_D) ? 'D' : ' ',
                  (tlb.tlb_lo0 & MIPS3_PG_G) ? 'G' : ' ',
                  (tlb.tlb_lo0 >> 3) & 7);
!             db_printf("Lo1=0x%09" PRIx64 " %c%c attr %x sz=%x\n",
!                 (uint64_t)mips_tlbpfn_to_paddr(tlb.tlb_lo1),
                  (tlb.tlb_lo1 & MIPS3_PG_D) ? 'D' : ' ',
                  (tlb.tlb_lo1 & MIPS3_PG_G) ? 'G' : ' ',
                  (tlb.tlb_lo1 >> 3) & 7,
***************
*** 395,402 ****
           * Cast the physical address -- some platforms, while
           * being ILP32, may be using 64-bit paddr_t's.
           */
!         db_printf("0x%lx -> 0x%qx\n", addr,
!             (unsigned long long) kvtophys(addr));
      } else
          printf("not a kernel virtual address\n");
  }
--- 396,403 ----
           * Cast the physical address -- some platforms, while
           * being ILP32, may be using 64-bit paddr_t's.
           */
!         db_printf("0x%lx -> 0x%" PRIx64 "\n", addr,
!             (uint64_t) kvtophys(addr));
      } else
          printf("not a kernel virtual address\n");
  }

-- 
Garrett D'Amore, Principal Software Engineer
Tadpole Computer / Computing Technologies Division,
General Dynamics C4 Systems
http://www.tadpolecomputer.com/
Phone: 951 325-2134  Fax: 951 325-2191