Matthew Orgass wrote:

> On 2005-11-18 simonb@wasabisystems.com wrote:
> 
> > I believe algor, evbmips and pmax get this right.  In these ports,
> > cpu_intr() calls a machine-specific *_iointr(), and all these
> > machine-specific functions all finish with an _splset() to reenable
> > any processed interrupts.
> 
>   No, pmax doesn't reenable processed interrupts (at least the 3min and
> 3max I looked at); it is (status & ~cause & MIPS_HARD_INT_MASK), which
> reenables the interrupts not processed.  Soft interrupts will then proceed
> without further altering the interrupt mask (and if any of the
> non-processed interrupts occur the processed interrupts will remain
> blocked until the other (potentially lower priority) interrupts complete.

Ok, pmax isn't right in this respect.  The other ports (algor, evbmips)
clear bits in cause as they're processed, then at the end use
(status & ~cause & MIPS_HARD_INT_MASK), where ~cause will be the
interrupts that now have been processed.  pmax just removes the clock
interrupt from cause, and re-enables that quickly, but doesn't reenable
any other interrupts before handling software interrupts.

The first bug (affecting most MIPS ports) is to set the master interrupt
enable bit (SR_INT_IE) if we arrive in cpu_intr() with only software
interrupts pending - the "(ipending & MIPS_INT_MASK_*) == 0" problem
that Tsutsui-san mentioned.  Note that algor, hpcmips, mipsco and
playstation2 don't use the "MI" MIPS software interrupts so we'll need
to check that they are all doing the right thing spl-wise when fixing
them.  playstation2 in particular seems to manage software interrupts via
one-shot timers, so I'm not even going to pretend to exactly understand
what it's doing there!

The second bug is to fix ports so that other interrupts are enabled
after processing. pmax is one, as discussed above.  Of the other ports
cobalt, mipsco (I think), newsmips, sbmips and sgimips look alright.
hpcmips I'm not sure about at a glance.  The vr version does play with
cause a little bit but I'm not sure exactly what it is doing, but tx
doesn't reenable any interrupts at all since cause isn't changed at all
before using ~cause in the _splset().

Simon.
--
Simon Burge                            <simonb@wasabisystems.com>
NetBSD Support and Service:         http://www.wasabisystems.com/