Subject: Re: PCI on MIPS big-endian?
To: Garrett D'Amore <>
From: Martin Husemann <>
List: port-mips
Date: 10/18/2005 21:49:40
On Tue, Oct 18, 2005 at 10:12:31AM -0700, Garrett D'Amore wrote:
> Basically, my understanding is that bus_space_read_XXX and 
> bus_space_write_XXX are supposed to provide implicit swapping of data, 
> whereas bus_space_read_stream_XXX and write_stream_XXX are supposed to 
> skip the swapping.


>  (As far as I can tell, wi(4) is the only device I 
> can find that depends on the _stream versions.)

There are few others that use it, but they are not very common.

My sgimips O2 has a PCI bus and is big endian, but the only device on it
currently is:

pci0 at macepci0 bus 0
pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
ahc0 at pci0 dev 1 function 0: Adaptec aic7880 Ultra SCSI adapter
mace: established interrupt 8 (level 0)
ahc0: interrupting at crime interrupt 8
ahc0: Using left over BIOS settings
ahc0: aic7880: Wide Channel A, SCSI Id=0, 16/253 SCBs
scsibus0 at ahc0: 16 targets, 8 luns per target

and ahc does not using streaming bus access.

I have a ath pci card that I can put into that machine (athhal_osdep.* uses
streaming bus access), but it will take a while untill I can test it
(need the card in another machine for now).
> The mips bus_space.h file #define's the stream_XXX versions to be the 
> same as the non-stream versions.

That is certainly wrong. Can we #ifdef this on endianess?