Subject: Re: PCI on MIPS big-endian?
To: None <email@example.com>
From: Garrett D'Amore <firstname.lastname@example.org>
Date: 10/18/2005 10:29:18
>>Doesn't the Au15xx series have built-in conventions for allowing automatic
>>byte ordering?. Wasn't the PCI interface in the Au15xx series was designed
>>for just such an occurrence?
>Yes, it sure does. I beg forgiveness for this advance, really I'm sorry.
>In the latest Linux 2.6 kernel, 'arch/mips/au1000/pb1500/board_setup.c'
>around line 138 you can see the selection between big and little endian
>to setup the PCI bus. I'm going to get flamed, I can feel it.
From what I can tell, this is "sort of correct".
This logic gets me the values (which is good), but it gives then the
wrong endianness. For example, pretty much all of the Linux PCI drivers
still use readw/readl/outw/outl which implicitly do the swapping in
software -- see the Linux source file include/asm-mips/io.h for details.
So my read is that the endianness bits you are referring to "fix up"
address lines so that PCI reads to non-aligned accesses (e.g. for 8-bit
or 16-bit reads) go to the "right" bytes in physical PCI memory. It
doesn't do anything to address the ordering of the bytes in the value
that is read.
Perhaps I'm being dense here, but my reading, and actual experimentation
on my Au1550 board, seem to confirm this. (I have PCI working on this
board, mostly. It works well enough for ath(4) at least.)