Subject: Re: PCI on MIPS big-endian?
To: Simon Burge <>
From: Garrett D'Amore <>
List: port-mips
Date: 10/18/2005 10:12:31
Simon Burge wrote:

>Hi Garrett,
>On Tue, Oct 18, 2005 at 09:27:53AM -0700, Garrett D'Amore wrote:
>>Just out of curiousity, has anyone else ever tried running NetBSD on a 
>>MIPS processor in big-endian mode with a PCI bus attached?  As far as I 
>>can tell, all of the bus_space_XXX methods in the mips tree are busted 
>>for that.  Am I missing something, or am I just breaking new ground 
>>here?  (I do have it working, but I had to cobble up my own bus_space 
>>headers, and such.)
>The MIPS Malta 4Kc (under evbmips) runs both big- and little-endian and
>can use the on-board PCI ethernet and USB just fine.
OK, I'm confused.  Because I cannot fnd anywhere where it deals with the 
fact that PCI bus is little endian.  Is it the case that the PCI 
controller on the Malta auto-swaps PCI memory accesses to match CPU 

Basically, my understanding is that bus_space_read_XXX and 
bus_space_write_XXX are supposed to provide implicit swapping of data, 
whereas bus_space_read_stream_XXX and write_stream_XXX are supposed to 
skip the swapping.  (As far as I can tell, wi(4) is the only device I 
can find that depends on the _stream versions.)

The mips bus_space.h file #define's the stream_XXX versions to be the 
same as the non-stream versions.

And, as I've mentioned already, I cannot see where the non-stream endian 
versions perform the logic to swap the bytes on multi-byte accesses.

    -- Garrett

>It also looks like one of the SGI models has a PCI bus, and all SGI are
>PS: I still haven't had a chance to look at your previous email about
>paddr_t and bus_space, but this email is a quick and easy one to reply
>to :-)
>Simon Burge                                   <>
>NetBSD Development, Support and Service: