Subject: Re: [Fwd: PTEbase register]
To: , Nigel Stephens <firstname.lastname@example.org>
From: Dominic Sweetman <email@example.com>
Date: 03/09/2005 19:18:10
My colleague Nigel Stephens forwarded your mail:
> PTEbase is an convenience register to make short TLB refilling
> exception handler.
Your terminology is a bit non-standard. The register is usually
called "Context", and its fields are PTEBase and BadVPN2.
> The decision is a mystery for me why KSEG2 TLB miss was not
> a part of R3000 TLB refill. They named it "UTLB miss"
Bear in mind that the R2000 was set up to run BSD4.2 Unix.
The UTLB miss handler was meant to be the shortest possible piece of
code which would handle the frequent event of a missing TLB
translation from user space. The fundamental trick to doing that was
locating a virtually-linear page table in kseg2, which was in fact
only sparsely mapped. But that trick requires the system to be able
to take a nested TLB miss from inside the UTLB miss handler.
The early BSD kernel made only relatively light use of kernel mapped
memory. The per-process data area was wired, so the biggest kseg2
consumer was the page-table.
In turn the page-table tended to be TLB-missed mainly by the nested
exception inside the UTLB handler - and that certainly couldn't be
sent back to the UTLB entry point without making the UTLB handler
complicated again, and spoiling everything.
So it made quite good sense to dispatch user-mode TLB misses to the
UTLB handler, and kernel-mode TLB misses to the main exception entry
> The R4000 designer changed their mind. They realized
> KSEG2 TLB miss should have been a part of fast TLB refill
> exception control path...
Well, not really. The R4000 designers figured out that they could
build a simpler exception system around the magic EXL bit, and still
handle the nested exception from the UTLB miss handler. (EXL and the
peculiar rules about how exceptions behave in its presence is the key
invention - and fairly clearly, the R2000 designer didn't think of it.)
In the R4000, the obvious thing to do is to distinguish TLB misses
according to whether EXL is already set.
Nothing in CP0 was ever explained... if anyone knows how EXL got
invented, I'd love to put that in the next edition of "See MIPS Run".