On Thu, Nov 04, 2004 at 07:38:38PM +0100, Markus W Kilbinger wrote:
> >>>>> "Manuel" == Manuel Bouyer <bouyer@antioche.eu.org> writes:
> 
>     Manuel> Could be a cache sync issue. What CPU is there in this box
>     Manuel> ? Also what devices do you use for disk and network I/O ?
> 
>     >> cpu0 at mainbus0: QED RM5200 CPU (0x28a0) Rev. 10.0 with built-in FPU Rev. 10.0
>     >> cpu0: 32KB/32B 2-way set-associative L1 Instruction cache, 48 TLB entries
>     >> cpu0: 32KB/32B 2-way set-associative write-back L1 Data cache
> 
>     Manuel> 32B lines, this matchs what you've reported.
> 
> Does this help (anybody) to understand what's going wrong here then?

Probably a bug in the cache management routines, but I can't tell more.
I'm not familiar with this part of code.

> 
>     >> 'tlp0' and 'viaide0' are all onboard devices.
> 
>     Manuel> tlp0 should have bus_dma related bugs, as it's known to
>     Manuel> work on alpha, sparc64, and others hardware where
>     Manuel> bus_dma_sync() isn't a NOP.
> 
> That means the tlp driver is buggy in cobalt mips machines?

No, sorry, there is a missing "no" here. As far as I know, the tlp driver
should be fine.

-- 
Manuel Bouyer <bouyer@antioche.eu.org>
     NetBSD: 26 ans d'experience feront toujours la difference
--